REG_CIAAPRA equ $bfe001
REG_VPOSR equ $dff004
REG_VHPOSR equ $dff006
REG_COL0 equ $dff180
REG_INTENA equ $dff09a
REG_INTENAR equ $dff01c
REG_INTREQ equ $dff09c
REG_INTREQR equ $dff01e
REG_DMACON equ $dff096
REG_DMACONR equ $dff002
REG_ADKCON equ $dff09e
REG_ADKCONR equ $dff010

REG_BPLCON0 equ $dff100
REG_BPLCON1 equ $dff102
REG_BPLCON2 equ $dff104

REG_BPL0PTH equ $dff0e0
REG_BPL1PTH equ $dff0e4
REG_BPL2PTH equ $dff0e8
REG_BPL3PTH equ $dff0ec
REG_BPL4PTH equ $dff0f0
REG_BPL5PTH equ $dff0f4

REG_BPL1MOD equ $dff108
REG_BPL2MOD equ $dff10a

REG_DIWSTART equ $dff08e
REG_DIWSTOP equ $dff090
REG_DDFSTART equ $dff092
REG_DDFSTOP equ $dff094

EXECBASE equ 4
EXEC_FORBID equ -132
EXEC_PERMIT equ -138

WIDTH equ 448
HEIGHT equ 384
BPLSIZE equ WIDTH/8*HEIGHT
MAX_VSCROLL equ HEIGHT-256
MAX_HSCROLL equ WIDTH-320
HMOD equ MAX_HSCROLL/8-2

start:
	move.l EXECBASE, a0
	jsr EXEC_FORBID(a0)

	move.w REG_DMACONR, prev_dmacon
	move.w #$01ff, REG_DMACON	; disable all DMA ops

	move.w REG_INTENAR, prev_intena
	move.w #$7fff, REG_INTENA	; disable intr

	move.w REG_INTREQR, prev_intreq
	move.w REG_ADKCONR, prev_adkcon

	move.w #$4200, REG_BPLCON0	; 4 bitplanes, composite color
	move.w #0, REG_BPLCON1		; hscroll 0
	move.w #HMOD, REG_BPL1MOD	; odd bpl modulo
	move.w #HMOD, REG_BPL2MOD	; even bpl modulo
	move.w #$2981, REG_DIWSTART	; window start (129,41)
	move.w #$29c1, REG_DIWSTOP	; window stop (449,297)
	move.w #$0030, REG_DDFSTART	; data fetch start
	move.w #$00d0, REG_DDFSTOP	; data fetch stop

	; populate palette
	move.l #REG_COL0, a0
	moveq #0, d0
paltop:	move.w d0, d1
	moveq #15, d2
	sub.w d1, d2
	lsl.w #8, d2
	or.w d0, d2
	move.w d2, (a0)+
	addi.w #1, d0
	cmp.w #16, d0
	bne paltop

	; fill framebuffer
	move.l #bpl0ptr, a0
	moveq #0, d4	; d4: current bitplane
	moveq #0, d5	; d5: bit accumulator
	moveq #8, d6	; d6: current bit-accumulator bit
fill_top:
	moveq #0, d3	; d3: y coord
fill_y:	moveq #0, d2	; d2: x coord
fill_x:	move.w d2, d0
	eor.w d3, d0	; d0 = x ^ y
	move.w d4, d1
	addi.w #2, d1
	lsr.w d1, d0	; bring bit of interest to position 0
	andi.w #1, d0	; and isolate it

	lsl.w #1, d5
	ori.w d0, d5
	subi.w #1, d6

	bne skipadv
	move.b d5, (a0)+
	moveq #0, d5
	moveq #8, d6
skipadv:
	addi.w #1, d2
	cmp.w #WIDTH, d2
	bne fill_x
	addi.w #1, d3
	cmp.w #HEIGHT, d3
	bne fill_y
	addi.w #1, d4
	cmp.w #4, d4
	bne fill_top

	bsr wait_vblank
	move.l #bpl0ptr, REG_BPL0PTH
	move.l #bpl1ptr, REG_BPL1PTH
	move.l #bpl2ptr, REG_BPL2PTH
	move.l #bpl3ptr, REG_BPL3PTH

	move.w #$8300, REG_DMACON	; enable bitplane and master DMA

mainloop:
	; exit on click
	btst.b #6, REG_CIAAPRA
	beq exit

	bsr wait_vblank

	; --- scrolling ---
	moveq #0, d0
	move.w vscroll, d0
	mulu #WIDTH/8, d0
	move.w hscroll, d1
	move.w d1, d2
	lsr.w #3, d1
	add.w d1, d0		; add hscroll>>4 pixels or hscroll>>3 bytes
	andi.w #$f, d2		; ... and keep the remaining bits in d2

	move.l #bpl0ptr, a0
	addi.l d0, a0
	move.l a0, REG_BPL0PTH
	addi.l #BPLSIZE, a0
	move.l a0, REG_BPL1PTH
	addi.l #BPLSIZE, a0
	move.l a0, REG_BPL2PTH
	addi.l #BPLSIZE, a0
	move.l a0, REG_BPL3PTH

	; set the 15 - hscroll%16 (d2) as pixel-fetch delay
	move.w d2, d1
	lsl.w #4, d1
	ori.w d1, d2
	not.b d2
	move.w d2, REG_BPLCON1

	; change vertical offset
	move.w vscroll, d0
	addi.w vscroll_dir, d0
	bne not0
	neg.w vscroll_dir
not0:	cmp.w #MAX_VSCROLL, d0
	bne notmax
	neg.w vscroll_dir
notmax: move.w d0, vscroll

	; change horizontal offset
	move.w hscroll, d0
	addi.w hscroll_dir, d0
	bne hnot0
	neg.w hscroll_dir
hnot0:	cmp.w #MAX_HSCROLL, d0
	bne hnotmax
	neg.w hscroll_dir
hnotmax:move.w d0, hscroll

	;addi.w #1, frameno
	bra mainloop

exit:
	; restore original values to modified registers
	or.w #$8000, prev_dmacon
	move.w #$7fff, REG_DMACON
	move.w prev_dmacon, REG_DMACON

	or.w #$8000, prev_intreq
	move.w #$7fff, REG_INTREQ
	move.w prev_intreq, REG_INTREQ

	or.w #$8000, prev_adkcon
	move.w #$7fff, REG_ADKCON
	move.w prev_adkcon, REG_ADKCON

	or.w #$8000, prev_intena
	move.w #$7fff, REG_INTENA
	move.w prev_intena, REG_INTENA

	move.l EXECBASE, a0
	jsr EXEC_PERMIT(a0)
	rts


wait_vblank:
	move.l REG_VPOSR, d0
	and.l #$1ff00, d0
	cmp.l #300<<8, d0
	bne.s wait_vblank
	rts

	Section bss,BSS
	CNOP 0,4
prev_intena ds.w 1
prev_dmacon ds.w 1
prev_intreq ds.w 1
prev_adkcon ds.w 1

	Section data,DATA
	CNOP 0,4
frameno dc.l 0
vscroll dc.w MAX_VSCROLL/2
hscroll dc.w 0
vscroll_dir dc.w 1
hscroll_dir dc.w 1

	Section cdata,DATA_C
	CNOP 0,4
bpl0ptr dcb.b BPLSIZE, 0	
bpl1ptr dcb.b BPLSIZE, 0
bpl2ptr dcb.b BPLSIZE, 0
bpl3ptr dcb.b BPLSIZE, 0